Output drivers are a class of circuits used, for example in integrated circuit (IC) chips, for purposes of driving a load with a high current drive. Generally speaking, small current driving transistors are used internally in the IC chip but cannot drive a heavy load. Output drivers are provided for outputting such signals externally from the IC with a high current driving capability and therefore can drive a heavy load. As such, output driver circuits are often referred to as "output buffers."
To achieve a high current drive, output buffers typically contain large MOSFET or MOS transistors. (Herein, as per common usage in the art, MOSFET or MOS refer to any insulated gate field effect transistors, preferably polycrystalline silicon gate field effect transistors, and not only metal oxide semiconductor field effect transistors.) Such large transistors present a noise problem for the IC. In particular, the output buffer transistors are connected to a high voltage V.sub.DD power supply bus and a low voltage V.sub.SS power supply bus. The output buffer transistors furthermore drive an output terminal in the form of a large area bonding pad that has a finite capacitance. During a high speed transition in logic value, the large output buffer transistors can produce a high current. This high current, in turn, can impress a noise voltage on the low and high power supply buses as a result of bonding wire, packaging and other inductances. (Note that the impressed voltage is given by v=L.multidot.di/dt, where v is the noise voltage, L is the inductance of the bonding wire, packaging, etc., and di/dt is the derivative of the current generated by the large driver transistors of the output buffer with respect to time. Thus, the more rapidly that the current of the large driver transistors of the output buffer varies in time, the larger the magnitude of the impressed noise signal.) This undesirable noise voltage on the high and low power supply buses is commonly referred to as "ground bounce."
A number of prior art solutions have been proposed to reduce "ground bounce" in output buffers. Of interest is a prior art output buffer 10 shown in FIG. 1 and disclosed in U.S. Pat. No. 4,987,324. As shown, a low current drive driver A and a high current drive driver B are provided for driving the output terminal pad T. The driver A is formed by a PMOS transistor Q1A and an NMOS transistor Q2A connected in a "push-pull inverter" configuration. Specifically, the PMOS transistor Q1A has its source connected to the high voltage V.sub.DD power supply bus, its drain connected to the output terminal pad T and its gate connected to an input. The transistor Q2A has its source connected to the low voltage V.sub.SS power supply bus, its drain connected to the drain of the transistor Q1A and to the output terminal pad T and its gate connected to the gate of transistor Q1A and the input. The connections of the sources of the transistors Q1A and Q2A to the high voltage V.sub.DD and low voltage V.sub.SS power supply buses, respectively, provide high voltage and low voltage biasing of the driver A with the high voltage V.sub.DD (e.g., 5 volts) and the low voltage V.sub.SS (e.g., ground or 0 volts). The driver A drives its output to a voltage which is a complement of the voltage inputted to its input. A predriver inverter E is provided which receives an input signal Vi and outputs a complement of the signal Vi to the input of the driver A.
The driver B is also an inverter formed from the PMOS transistor Q1B and the NMOS transistor Q2B which have their drains connected to the output terminal pad T. The source of the transistor Q1B is connected to the high voltage V.sub.DD power supply bus and the source of the transistor Q2B is connected to the low voltage V.sub.SS power supply bus. Unlike the driver A, the driver B has two predriver inverters C and D. The inverter C receives the input signal Vi and outputs the complement of this signal to the gate of the transistor Q1B. The inverter D receives the input signal Vi and outputs the complement of this signal to the gate of the transistor Q2B.
During steady-state operation, when the input signal Vi is a logic `0` (low voltage level V.sub.SS), the inverters E, D and C each output a logic `1` value (high voltage level V.sub.DD) to the inputs of the transistors Q1A, Q2A, Q1B and Q2B. Transistors Q1A and Q1B, being PMOS transistors, are off and transistors Q2A and Q2B, being NMOS transistors, are on. As such, the transistors Q2A and Q2B both sink any current on the output terminal pad T to the low voltage V.sub.SS power supply bus, thereby maintaining the voltage level of the output terminal pad T at V.sub.SS. On the other hand, when the input signal Vi is a logic value `1` (high voltage level V.sub.DD), the inverters C, D and E output a logic value `0` (low voltage level V.sub.SS). The transistors Q2A and Q2B, being NMOS transistors, are off and transistors Q1A and Q1B, being PMOS transistors, are on. As such, the transistors Q1A and Q1B supply a current to the output terminal pad T, thereby maintaining the voltage level of the output terminal pad T at V.sub.DD.
As noted above, ground bounce is an effect that occurs during a transition in logic value, i.e., from logic `0` to logic `1`, or logic `1` to logic `0`, of the input signal Vi (which results in a transition in corresponding voltage level of the output terminal pad T from V.sub.SS to V.sub.DD or from V.sub.DD to V.sub.SS, respectively). To reduce ground bounce, the driver A is provided with smaller sized (i.e., smaller channel width) transistors Q1A and Q2A than the transistors Q2A and Q2B provided in the driver B. Furthermore, the logic threshold voltages or switching voltages of the inverters C, D and E are selected to cause each inverter to switch, i.e., transition its output voltage, at a different time. This can be better understood with reference to FIG. 2. Suppose that the switching voltages of the inverters C, D and E are chosen to be 3.7, 1.1 and 2.5 volts, respectively. As shown, the input signal Vi begins to transition from logic `0` (voltage level V.sub.SS =0) to logic `1` (voltage level V.sub.DD =5) at time t0. At time t1, the voltage level of Vi reaches 1.1 volts thereby triggering inverter D to transition its output from logic value `1` to logic `0`. As a result, Q2B begins to turn off. At time t2, the voltage Vi reaches 2.5 volts thereby triggering inverter E to transition its output logic value from `1` to `0`. As a result, Q1A begins to turn on and Q2A begins to turn off. Finally at time t3, Vi reaches 3.7 volts thereby triggering inverter C to transition its output logic value from `1` to `0`. As a result, Q1B begins to turn on. The net effect is that first Q2B turns off at time t1, then Q1A turns on while Q2A turns off at time t2, followed by Q1B turning on at time t3. Thus, the turn on of the larger PMOS transistor Q1B is delayed until after the smaller PMOS transistor Q1A turns on. This is advantageous because the smaller transistor Q1A has a lower current driving capability. Initially, when Q1A turns on, the voltage of the output terminal pad is 0. The transistor Q1A slowly charges up the output terminal pad. Because of the limited current drive of the transistor Q1A and the relatively slow voltage change of the output terminal pad T, little ground bounce is produced. Later, the transistor Q1B turns on with a higher current drive capability. However, at this point, the output terminal pad is partially charged and therefore a rapidly changing current drive is avoided, despite the output terminal pad T being driven by a high current drive transistor Q1B. Because a rapid current change is avoided, ground bounce is suppressed.
Likewise, when the input signal transitions from logic `1` to logic `0`, the inverters change their outputted logic values from logic `1` to logic `0` successively in the order of inverter C first, followed by inverter E followed by inverter D. The net effect is that Q1B turns off first, then Q1A turns off and Q2A turns on followed finally by Q2B turning on. Because smaller transistor Q2A turns on first, it begins to slowly discharge the output pad T with its (relatively) low current drive capability. Then, larger transistor Q2B turns on. However, the output terminal pad T is already partly discharged. Thus, Q2B drives the output terminal pad T with a less rapidly changing current. Again, ground bounce is reduced.
While the output buffer 10 can suppress ground bounce, it is not suitable for all applications. For example, in certain applications, the current drive capacity of both the small and large drivers is relatively high. For example, to achieve a requisite current drive in some applications, the transistor Q1A may have a channel width of 200 .mu.m and the transistor Q1B may have a channel width of 1000 .mu.m. As indicated in FIG. 2, during a transition, both transistors Q1A and Q2A are simultaneously on. This produces a short circuit path between the high power supply bus and the low power supply bus. If the transistors Q1A and Q2A are large, then a high short circuit current may be produced which damages the IC.
Second, consider an example where Q1B has a channel width of 800 .mu.m and Q2B has a channel width of 400 m. During a transition in input signal Vi logic value from `0` to `1`, the delay in turn on time between transistors Q1B and Q1A is controlled by the relative switching voltages of predrivers E and C. Likewise, during a transition in input signal Vi logic value from `1` to `0`, the delay in turn on time between the transistors Q2B and Q2A is controlled by the relative switching voltages of predrivers E and D. However, such delays are not sufficient to reduce ground bounce in certain applications for such large transistors Q1B and Q2B.
FIG. 3 shows a low speed output buffer 20 proposed by Intel.TM., a semiconductor manufacturer located in Santa Clara California. An output pad Dx is selectively driven by PMOS pull-up driver transistor P4', having a source connected to the high voltage V.sub.DD power supply bus and a drain connected to the output pad Dx, or NMOS pull-down driver transistor N4' having a source connected to the low voltage V.sub.SS power supply bus and a drain connected to the output pad Dx. PMOS quick turn off transistor P3' receives a signal P.sub.-- EN. When P.sub.-- EN is logic `0`, P3' turns on and drives the gate of P4' to the high voltage level V.sub.DD thereby turning off P4'. Otherwise, when P.sub.-- EN is logic `1`, P3' is off and does not drive the gate of P4' to any voltage level. Likewise, NMOS quick turn off transistor N3' receives a signal N.sub.-- EN. When N.sub.-- EN is logic `1`, N4' quickly turns on and drives the gate of N4' to the low voltage level V.sub.SS, thereby turning off N4'. Otherwise, when N.sub.-- EN is logic `0`, N3' is off and does not drive the gate of N4' to any voltage level.
Connected to the gates of P4' and N4' are analog differential amplifiers 22 and 24, respectively. The amplifier 22 receives the signal P.sub.-- EN as an enable signal and the amplifier 24 also receives the signal N.sub.-- EN as an enable signal. The positive (noninverting) inputs of each amplifier 22 and 24 are connected together. Each amplifier 22 and 24 receives a signal CNTR at a negative (inverting) input. The voltage level of CNTR is selected to cause amplifiers 22 and 24 to selectively output a low or negative voltage or high or positive voltage, depending on the voltage applied to the positive inputs (as described in greater detail below). Also connected to the positive inputs of the amplifiers 22 and 24 is the drain of a PMOS transistor P2' and the drain of an NMOS transistor N2'. The source of the transistor P2', in turn is connected to the drain of a transistor P1'. The source of the transistor P1' is connected to the high voltage V.sub.DD power supply bus. The source of transistor N2' is connected to the drain of a transistor N1'. The source of the transistor N1' is connected to the low voltage V.sub.SS power supply bus.
The gate of the transistor N2' receives the signal P.sub.-- EN and the gate of the transistor P2' receives the signal N.sub.-- EN. The gate of the transistor P1' receives the steady voltage PBIAS. PBIAS is selected so that transistor P1' produces a particular maximum current for reasons discussed below. Likewise, the gate of the transistor N1' receives the steady voltage NBIAS, selected so that transistor N1' produces a particular maximum current. Connected between the common positive input connection of the amplifiers 22 and 24 and the output terminal pad Dx is a capacitor C1 with a particular capacitance.
The operation of the output buffer 20 is as follows. When the data to be outputted is logic `0`, the signal N.sub.-- EN is a logic `0` and the signal P.sub.-- EN is a logic `0`. As a result, amplifier 22 is disabled because it does not receive a high voltage of signal P.sub.-- EN. P3' is on and maintains the voltage on the gate of P4' at a high level. Thus P4' remains off. N2' is off but P2' is on. Therefore, P1' and P2' maintain the charge on C1 at a high voltage level (which is less than V.sub.DD). The high voltage level of C1, also inputted to the positive input of amplifier 24 exceeds the voltage level inputted to the negative input of amplifier 24 (on signal CNTR). Thus, amplifier 24 outputs a positive voltage level to the gate of N4'. N3' is off and does not drive the gate of N4'. As such, N4' remains on and maintains the voltage of the output terminal pad Dx at a low voltage level V.sub.SS.
Now consider the case where a logic `1` is to be outputted. Both P.sub.-- EN and N.sub.-- EN are logic `1`. Amplifier 24 is disabled because it does not receive a low voltage of signal N.sub.-- EN. N3' is on and drives the gate of N4' thereby maintaining the voltage level of the gate of N4' at a low level. As such N4' remains off. P2' is off and N2' is on. As such, N1' and N2' maintain the charge on C1 at a low voltage level (which is greater than V.sub.SS). This low voltage level, in turn, is inputted to the positive input of the amplifier 22. Because the low voltage level is less than the voltage level received at the negative input of the amplifier 22 (i.e., supplied by the signal CNTR), the amplifier 22 outputs a low or negative voltage. P3' is off and does not drive the gate of P4'. Since the gate of P4' receives only the low voltage of the amplifier 22, P4' remains on and maintains the voltage of the output terminal at a high voltage level V.sub.DD.
Consider now a transition in logic value from `0` to `1`. In such a case, both P.sub.-- EN and N.sub.-- EN transition in logic value from `0` to `1`. P3' turns off, N3' turns on and amplifier 24 turns off. As such, N4' turns off quickly. P2' turns off and N2' turns on. Thus, N1' and N2' gradually discharge the capacitor C1. Capacitor C1 discharges over a delay period. As C1 discharges, the voltage applied to the positive inputs of the amplifiers 22 and 24 decreases and the voltage outputted from the amplifier 22 gradually decreases. This causes P4' to gradually turn on. As P4' turns on, it gradually charges the output terminal pad Dx to a high voltage.
Consider now a transition in logic value from `1` to `0`. In such a case, both P.sub.-- EN and N.sub.-- EN transition in logic value from `1` to `0`. This causes N3' to turn off P3' to turn on and amplifier 22 to turn off. As such, P4' turns off quickly. P2' turns on and N2' turns off. As a result, P2' and P1' begin to charge C1 over a delay period. As C1 charges, the voltage supplied to the positive inputs of the amplifier 22 gradually increases. This causes the voltage outputted from the amplifier 22 to increase gradually, which output voltage, in turn, gradually turns on N4'. As N4' turns on, it gradually discharges the output terminal pad Dx to a low voltage.
Thus, the low speed output buffer 20 has an advantage of a gradual transition thereby reducing ground bounce and stabilizing the rise and fall times of the output terminal pad. The output buffer 20, however, has two disadvantages. First, the capacitor C1 is difficult to implement in an IC. Because the voltage of the two terminals of C1 is neither at V.sub.DD or V.sub.SS, the capacitor C1 must be implemented from two separate layers of polycrystalline silicon separated by a dielectric layer, especially when C1 must remain within precise tolerances. Thus, the output buffer 20 is more expensive and complex. Second, the output buffer 20 has a high power consumption.
FIG. 4 shows another output buffer circuit 50 disclosed in U.S. Pat. No. 4,820,942. As shown, the complement of an output signal, an OE signal and the complement of the OE signal are received at an AC or transient driver 52 and a DC or steady state driver 54. In this case, the AC driver 52 includes two weak current driving NMOS transistors Q1 and Q2 and the DC driver 54 includes two strong current driving NMOS transistors Q3 and Q4. Gates G1-G5 are provided which, in response to a logic `1` valued output signal (logic `0` valued complement of the output signal), enable the transistor Q1 to drive the output terminal 59 to a high voltage or logic `1` value (and disable the transistor Q2). The gates G1-G5 furthermore, in response to a logic `1` valued output signal (logic `1` valued complement of the output signal), enable the transistor Q2 to drive the output terminal 59 to a low voltage or logic `0` value (and disable the transistor Q1). When OE is logic `0`, both transistors Q1 and Q2 are disabled.
Also provided is a delay circuit 56 connected between an output of a NOR gate G9 and an input of a NOR gate G8. Likewise, a delay circuit 58 is connected between an output of the NOR gate G8 and an input of the NOR gate G9. The NOR gates G8 and G9 also receive the complement of OE. The gate G9 receives the output signal, via inverters G6 and G7, as an input. The gate G8 receives the complement of the output signal, via inverter G6, as an input. The output of the gate G8 is connected to the gate of transistor Q3 and the output of gate G9 is connected to the gate of transistor Q4. When the complement of OE is a logic `1`, both gates G8 and G9 output a logic `0` or low voltage which disables both the transistors Q3 and Q4.
Consider first the case where the output signal is a logic `1` and thus the complement of the output signal is logic `0`. The gate G8 receives logic `0` on each of its inputs (OE complement, output signal complement and output of gate G9) and therefore outputs a logic `1`. The gate G9 receives the logic `1` output signal directly, and the logic `1` output of the gate G8, via delay circuit 58. Therefore, the gate G9 outputs a logic `0`. Thus, the AC transistor Q1 and DC transistor Q3 are on. When the output signal transitions from logic `1` to logic `2`, the transistors Q1 and Q3 are turned off quickly and the AC transistor Q2 is turned on quickly. The DC transistor Q3 turns off quickly because the change in logic value of the output signal changes one of its inputs to logic `1` without delay, thereby resulting in the NOR gate G8 quickly changing to outputting a logic `0`. Thus, initially, only the small driving capacity AC transistor Q2 turns on to slowly discharge the output terminal 59 thereby driving it to a low voltage (logic `0`). The transition in logic value of the NOR gate G8 from logic `1` to logic `0` takes a pre determined delay to propagate through the delay 58 before it is received at the gate G9. Eventually, after the predetermined delay period of the delay 58, the logic gate G9 receives the logic `1` output of the gate G8 from the delay 58. This changes the output of the NOR gate G9 to logic `1` (because now the gate G9 receives all logic `0` values as inputs). Thus, after the delay period of the delay circuit 58, the gate G9 changes its output to logic `1` thereby enabling the DC transistor Q4. Thus, eventually, DC transistor Q4 turns on and assists AC transistor Q2 in driving the output terminal 59 to a low voltage. Transistors Q2 and Q4 remain on thereafter to maintain the output terminal 59 voltage at a low voltage (logic `0`).
Consider now the case where the output signal initially is logic `0` and thus the complement of the output signal is logic `1`. The AC transistor Q2 is on and the AC transistor Q1 is off. Each input to the gate G9 is a logic `0`. Thus, the gate G9 outputs a logic `1` to the DC transistor Q4 which is on. The gate G8 receives two logic `1` inputs (output of gate G9 and complement of output signal) and thus outputs a logic `0`. Thus, the DC transistor Q3 is off When the output signal transitions to the logic `1` state, the AC transistor Q2 quickly turns off and the AC transistor Q1 quickly turns on. The gate G9 quickly transitions its output to logic `0` thereby quickly turning off the DC transistor Q4. Thus, initially, only the small driving capacity AC transistor Q1 is turned on for slowly charging up the output terminal 59 and driving it to a high voltage (logic `1`). The delay circuit 56 eventually propagates the logic `0` output of the gate G9, after a predetermined delay, to the gate G8. Likewise, the gate G8 receives the complement of the output signal, namely, logic `0`. Since all inputs to the gate G8 are now logic `0`, the gate G8 transitions its output to a logic `1` (after the delay of the delay circuit 56). This turns on DC transistor Q3 which assists in driving the terminal to a high voltage (logic `1`). The transistors Q1 and Q3 thereafter remain on to maintain the output terminal 59 voltage at a high voltage.
By delaying the turn on of the large capacity (DC) transistors Q3 and Q4, the production of ground bounce in the output buffer is reduced. However, the output buffer 50 is not suitable for all applications. For example, a new standard called the Universal Serial Bus (USB), was recently approved for computer equipment peripherals. According to USB, devices can communicate data at a full speed of 12 Mbit/sec or a low speed of 1.5 Mbit/sec. The USB standard specifies precise rise and fall rates of output voltage levels of USB compliant devices of about 4-20 nsec for full speed data communication but only 75-300 nsec for low speed communication. This presents a problem for ground bounce suppressing output buffers which are typically designed with slew rates for only a single particular data communication rate. For example, the delay circuits 56 and 58 in the output buffer 50 are formed as a tandem connection of multiple inverters. The delay achieved by such delay circuits 56 and 58 is very sensitive to the high voltage V.sub.DD level of the high voltage power supply bus (which usually is designed to vary up to 10% of the desired level), operating temperature and process variation. Therefore, it is difficult to design a delay circuit 56 or 58 that achieves an adequate delay during low speed operation, e.g., in a USB IC application wherein both full and low speed data communication must be accommodated. Furthermore, to achieve a 75 nsec delay, as would be necessary to comply with USB specified operating conditions, the delay circuits 56 and 58 would occupy a large amount of precious area on the IC chip. As such, the output buffer 50 is not suitable for a USB IC application.
It is an object of the present invention to overcome the disadvantages of the prior art.